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Integrated Circuit Systems, Inc.
ICS9150-01
Pentium ProTM and SDRAM Frequency Generator
General Description
The ICS9150-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. An output enable is provided for testability. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. * * * * * * * * * *
Features
Generates five processor, six bus, one 14.31818MHz and 16 SDRAM clocks. Synchronous clocks skew matched to 250 ps window on PCLKs and 500ps window on BCLKs Test clock mode eases system design Selectable multiplying ratios Custom configurations available Output frequency ranges to 100 MHz (depending on option) 3.0V - 3.7V supply range PC serial configuration interface Power Management Control Input pins 56-pin SSOP package
Pin Configuration Block Diagram
56-Pin SSOP
Functionality
FS0
0 1
C P U C LK , S D RA M ( M Hz) 60.0 66.6
X 1 , R EF ( M Hz)
P C I C LK ( M Hz)
14.318 14.318
30 33.3
Pentium is a trademark of Intel Corporation
9150-01 RevE 4/25/01
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9150-01
Pin Descriptions
PI N N U M B E R 3 4, 10, 17, 23, 31, 34, 40, 47, 53 5 6 29 8 9, 11, 12, 13 14, 16 30 27 28 1, 7, 15, 20, 26, 37, 43 50, 56 18, 19, 21, 22, 24, 25, 32, 33, 35, 36, 38, 39, 41, 42, 44, 45 2, 54, 55 46, 48, 49, 51, 52 32 33 PI N N A M E REF0 GN D X1 X2 MO DE PC IC LK _F PC IC LK (0:5) FS0 SDATA SC LK VDD2, VDD1, VDD, VDD3 VDDL2, VDDL1 SDRAM (0:11) (14:15) IO AP IC (0 :2 ) C P UC LK (0 :4 ) S DRAM1 3 C P U_ S TO P # S DRAM1 2 P C I_ S TO P # TYPE D E S C R I PT I O N O UT 14.318 MHz reference clock outputs. PWR IN O UT IN O UT O UT IN IN IN PWR PWR O UT O UT O UT O UT IN O UT IN Ground. 14.318MHz input. Has internal load cap. C rystal output. Has internal load cap and feedback resistor to X1 Mode select pin for enabling power management features, has pullup. Free running BUS clock during PC I_STO P#=0. BUS clock outputs. Select pin for enabling 66.6 MHz or 60 MHz. C PU/SDRAM clock frequency Serial data in for serial config port. C lock input for serial config port. N ominal 3.3V power supply, see power groups for function. C PU and IO APIC clock buffer power supply, either 2.5 or 3.3V nominal. SDRAM clocks (60/66.6MHz) IO APIC clock output. (14.31818 MHz) Poweredby VDDL1 C PU O utput clocks. Powered by VDDL2 (60 or 66.6MHz) SDRAM clock (60/66.6 MHz) Halts C PUC LK clocks at logic "0" level when low. SDRAM clock (60/66.6 MHz) Halts PC IC LK (0:5) at logic "0" level when low.
Power Groups
VDD = Supply for PLL core VDD1 = REF 0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:11) (14:15), SDRAM13/CPU_STOP#, SDRAM12/PCI_STOP# VDDL1 = IOAPIC (0:2) VDDL2 = CPUCLK (0:4)
2
ICS9150-01
Power-On Conditions
S EL 6 6 / 6 0 # M O DE P IN # 52, 51, 49, 48, 46 45, 44, 42, 41, 39, 38, 36, 35, 22, 21, 19, 18, 33, 32, 25, 24 9, 11, 12, 13, 14, 16, 8 52, 51, 49, 48, 46 45, 44, 42, 41, 39, 3 8 , 3 6 , 3 5 , 2 2 , 2 1, 19, 18, 33, 32, 25, 24 9, 11, 12, 13, 14, 16, 8 52, 51, 49, 48, 46 45, 44, 42, 41, 39, 38, 36, 35, 22, 21, 19, 18, 25, 24 33 32 52, 51, 49, 48, 46 45, 44, 42, 41, 39, 3 8 , 3 6 , 3 5 , 2 2 , 2 1, 19, 18, 25, 24 33 32 D ES C R I P TI O N CPUCLK s SDRAM PCICLK s CPUCLK s SDRAM PCICLK s CPUCLK s SDRAM PCI_STO P# CPU_STO P# CPUCLK s SDRAM PCI_STO P# CPU_STO P# F U N C TI O N 66.6 MHz - w/serial config enable/disable 66.6 MHz - All SDRAM outputs 33.3 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable 30 MHz - w/serial config enable/disable 66.6 MHz - w/serial config enable/disable 66.6 MHz - All SDRAM outputs Power Management, PC I (0:5) clocks stopped when low Power Managemen, C PU clocks stopped when low 60 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable Power Management, PC I (0:5) clocks stopped when low Power Managemen, C PU clocks stopped when low
1
1
0
1
1
0
0
0
Example: a) if MODE = 1, pins 33 and 32 are configured as SDRAM12, and SDRAM13 respectively. b) if MODE = 0, pins 33 and 32 are configured as PCI_STOP#, and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and "on" condition. The frequencies that are then produced are on the FS and MODE pin as shown in the table below.
C LO C K R EF 0 I O AP I C ( 0 :2 )
DEFAULT C O N DI TI O N AT P O W ER- UP 1 4 . 3 1 8 1 8 M Hz 1 4 . 3 1 8 1 8 M Hz
3
ICS9150-01
Technical Pin Function Descriptions
VDD(1,2,3) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, and SDRAM(0:7). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL1,2 This is the power supplies for the CPUCLK and IOAPCI output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. CPUCLK (0:4) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks are controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. SDRAM(0:15) These Output Clocks are use to drive Dynamic RAM's and are low skew copies of the CPU Clocks. The voltage swing of the SDRAM's output is controlled by the supply voltage that is applied to VDD3 of the device, operates at 3.3 volts. IOAPIC (0:2) These Outputs are fixed frequency Output Clocks that run at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. REF0 The REF Output is a fixed frequency Clock that runs at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equal to PCICLK(0:5) and is FREE RUNNING, and will not be stopped by PCI_STP#. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency. FS0 This Input pin controls the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. If a logic "1" value is present on this pin, the 66.6 MHz Clock will be selected. If a logic "0" is used, the 60MHz frequency will be selected. (This is the Power Management Mode) MODE This Input pin is used to select the Input function of the I/O pins. An active Low will place the I/O pins in the Input mode and enable those stop clock functions. (This is the Power Management Mode) CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLK's will have a turn ON latency of at least 3 CPU clocks. This input pin only valid when MODE=0 (Power Management Mode) PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not effect PCICLK_F nor any other outputs. This input pin only valid when MODE=0 (Power Management Mode) I2C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C specification in Philips I2C Peripherals Data Handbook (1996) should be followed.
4
ICS9150-01
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte.
Clock Generator Address (7 bits) A(6:0) & R/W# D2(H) ACK + 8 bits dummy command code + 8 bits dummy Byte count
ACK
ACK
Then Byte 0, 1, 2, etc in sequence until STOP.
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB PIIX4 protocol.
Clock Generator Address (7 bits) A(6:0) & R/W# D3(H) ACK Byte 0 ACK Byte 1 ACK
Byte 0, 1, 2, etc in sequence until STOP.
C. D. E. F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches maintain all prior programming information. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default to a 1 (Enabled output state)
G . H.
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default = 0)
BI T Bit 7 Bit 6 Bit 5 P IN # Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D ES C R I P TI O N Reserved Must b e 0 fo r no rmal o p eratio n Must b e 0 fo r no rmal o p eratio n In S p read S p ectrum, C o ntro ls typ e (0 =centered , 1=d o wn sp read ) Must b e 0 fo r no rmal o p eratio n In S p read S p ectrum, C o ntro ls C o ntro ls S p read ing % (0 = 1 . 8 %, 1 = 0 . 6 %) Reserved Reserved Bit0 Bit1 1 - Tri- S ta te 1 0 - S p re a d S p e c trum Ena b le 1 1 - Te s tmo d e 0 0 - N o rma l o p e ra tio n 0 P WD 0 0 0
0 0 0 0 0
Note: PWD = Power-Up Default I2C is a trademark of Philips Corporation
-
5
ICS9150-01
Select Functions
F UN C TIO N DES C RIP TIO N Tri - State Test Mode O UTP UTS C PU Hi- Z TCLK/21 P C I, P C I_ F Hi- Z TCLK/41 S DRAM Hi- Z TCLK/21 REF Hi- Z TCLK1 IO AP IC Hi- Z TCLK1
Notes: 1. REF is a test clock on the X1 inputs during test mode.
Byte 1: CPU Clock Register
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P IN # 46 48 49 51 52 PWD 1 1 1 1 1 1 1 1 D ES C R I P TI O N Reserved Reserved Reserved C PUC LK 4 (Act/Inact) C PUC LK 3 (Act/Inact) C PUC LK 2 (Act/Inact) C PUC LK 1 (Act/Inact) C PUC LK 0 (Act/Inact)
Byte 2: PCICLK Clock Register
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P IN # 8 16 14 13 12 11 9 P WD 1 1 1 1 1 1 1 1 D ES C R I P TI O N Reserved PC IC LK _F (Act/Inact) PC IC LK 5 (Act/Inact) PC IC LK 4 (Act/Inact) PC IC LK 3 (Act/Inact) PC IC LK 2 (Act/Inact) PC IC LK 1 (Act/Inact) PC IC LK 0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 3: SDRAM Clock Register
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P IN # 35 36 38 39 41 42 44 45 PWD 1 1 1 1 1 1 1 1 D ES C R I P TI O N SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Clock Register
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P IN # 24 25 32 33 18 19 21 22 P WD 1 1 1 1 1 1 1 1 D ES C R I P TI O N SDRAM15 (Act/Inact) SDRAM14 (Act/Inact) SDRAM13 (Act/Inact) Desktop O nly SDRAM12 (Act/Inact) Desktop O nly SDRAM11 (Act/Inact) SDRAM10 (Act/Inact) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
6
ICS9150-01
Byte 5: Peripheral Clock Register
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P IN # 2 54 55 3 P WD 1 1 1 1 1 1 1 1 D ES C R I P TI O N Reserved IO APIC 2 (Act/Inact) IO APIC 1 (Act/Inact) IO APIC 0 (Act/Inact) Reserved Reserved Reserved REF0 (Act/Inact)
Byte 6: Optional Register for Future
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P IN # P WD 1 1 1 1 1 1 1 1 D ES C R I P TI O N Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications.
Power Management
Clock Enable Configuration
O ther C lo ck s, S DRAM, REF, IO AP IC s Running Running Running Running
C P U_ S TO P # 0 0 1 1
P C I_ S TO P # 0 1 0 1
C P UC LK Low Low 66.6/60 MHz 66.6/60 MHz
P C IC LK Low 33.3/30 MHz Low 33.3/30 MHz
C rystal Running Running Running Running
VC O s Running Running Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9150-01 Power Management Requirements
Latency N o. of rising edges of free running PC IC LK 1 1 1 1
SIGN AL C PU_ STO P# PC I_STO P#
SIGN AL STATE 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
7
ICS9150-01
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9150-01. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9150-01. 3. All other clocks continue to run undisturbed. 4. PCI_STOP# is shown in a high (true) state.
8
ICS9150-01
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9150-01. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9150-01 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9150 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9150. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
9
ICS9150-01
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Outputs Disabled Supply Current Input Capacitance1 Transition Time1 Settling Time
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3OE CIN CINX Ttrans Ts TSTAB TCPU-SDRAM2
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V
0.1 2.0 -100 75 18
MAX UNITS VDD+0.3 V 0.8 V 5 A A A 95 25 5 45 3 mA mA pF pF ms ms 3 500 4 ms ps ns ps
27
36 5 5 200
Clk Stabilization Skew1
TCPU-PCI2 VT = 1.5 V TREF-IOAPIC VT = 1.5 V
1
2 900
10
ICS9150-01
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1
1
SYMBOL CONDITIONS IDD2.5OP CL = 0 pF; Select @ 66M TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads TREF-IOAPIC VT = 1.5 V; VTL = 1.25 V; CPU Leads
MIN 6
TYP 8 250
MAX 9.5 500 4
UNITS mA ps ns ps
1
2 860
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL
1 RDSP 2B 1 RDSN2B
CONDITIONS VO = VDD *(0.5) VO = VDD *(0.5) IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 15 15 2
TYP
MAX UNITS 45 45 V V mA mA ns ns % ps ps ps ps
VOH2B VOL2B IOH2B IOL2B tr2B tf2B
1 1
19
2.6 0.3 -25 26 1.7 1.5
0.4 -16 2 2 55 250 250 150 +250
1 d t2B
45
50 60 150 30
tsk2B
1
1 tjcyc-cyc2B
tj1s2B
1 1
tjabs2B
-250
80
Guarenteed by design, not 100% tested in production.
11
ICS9150-01
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL
1 RDSP 4B 1 RDSN4B
CONDITIONS VO = VDD *(0.5) VO = VDD *(0.5) IOH = -18 mA IOL = 18 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 10 10 2
TYP
MAX UNITS 30 30 V V mA mA ns ns % ps 400 1000 ps ps
VOH4\B VOL4B IOH4B IOL4B tr4B tf4B
1 1
19
2.4 0.45 -25 26 1.4 1.2
0.5 -16 1.6 1.6 60
1 d t4B 1 tjcyc-cyc4B
40
54 1400 300
tj1s4B
1
1 tjabs4B
-1000
800
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP 7 RDSN7 VOH7 VOL7 IOH7 IOL7 Tr7 Tf7 Dt7
1 1 1
CONDITIONS VO = VDD *(0.5) VO = VDD *(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 10 10 2.6
TYP
42
2.75 0.3 -62 50 0.9 0.9
MAX UNITS 24 24 V 0.4 V -54 mA mA 2 2 60 ns ns % ps ps 1000 ps
40
54 1400 350
1 tjcyc-cyc7B
tj1s7B
1
1 tjabs7B
-1000
900
Guarenteed by design, not 100% tested in production.
12
ICS9150-01
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP 1
1 1
CONDITIONS VO = VDD *(0.5) VO = VDD *(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.6
TYP
MAX UNITS 55 55 V V mA mA ns ns % ps ps ps
RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1 1 1 1
40
3.1 0.15 -65 54 1.5 1.4
0.4 -54 2 2 55 500 150 250
dt1
45
50 200 10
tsk1
tj1s1
tjabs1
1
-250
65
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP 3
1 1
CONDITIONS VO = VDD *(0.5) VO = VDD *(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.6
TYP
MAX UNITS 24 24 V V mA mA ns ns % ps ps ps
RDSN3 VOH3 VOL3 IOH3 IOL3 Tr3 Tf3 Dt3
1 1 1 1
40
2.8 0.3 -67 55 1.5 1.4
0.4 -54 2 2 55 500 150 250
45
50 200 50
Tsk3
Tj1s3
1 1
Tjabs3
-250
100
Guarenteed by design, not 100% tested in production.
13
ICS9150-01
N
c
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 N SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10 -0 0 3 4
VARIATIONS D mm. MIN MAX 18.31 18.55
D (inch) MIN .720 MAX .730
R ef erenc e D o c.: J E D E C P ub licat io n 9 5, M O -118
300 mil SSOP Package
Ordering Information
ICS9150F-01
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type Prefix ICS, AV = Standard Device
14
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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